Associate Professor Peter Sutton
Associate Professor

Peter Sutton

Email: 
Phone: 
+61 7 336 54854

Background

Associate Professor Peter Sutton's research interests are in Engineering Education, Embedded Computing Systems and Reconfigurable Computing

Associate Professor Peter Sutton has worked, studied and taught in the area of computer systems since completing his undergraduate studies in 1990. His particular research interests are in Engineering Education, Embedded System Design Software, Electronic Design Automation, and Reconfigurable Computing Systems.

Availability

Associate Professor Peter Sutton is:
Available for supervision
Media expert

Fields of research

Electronics, sensors and digital hardware Engineering

Qualifications

  • Bachelor of Science, The University of Queensland
  • Bachelor (Honours) of Engineering, The University of Queensland
  • Masters (Coursework) of Science, Carnegie Mellon University
  • Doctor of Philosophy, Carnegie Mellon University

Research interests

  • Engineering Education

  • Embedded System Development

  • Reconfigurable Computer Systems

Search Professor Peter Sutton’s works on UQ eSpace

38 works between 1991 and 2021
All (38) Journal Article (2) Conference Publication (36)

1 - 20 of 38 works

2021

Conference Publication

Managing Hands-on Electrical and Computer Engineering Labs during the COVID-19 Pandemic

Wijenayake, Chamith, D'souza, Matthew, Khatamianfar, Arash, Bialkowski, Konstanty, Ros, Montserrat and Sutton, Peter (2021). Managing Hands-on Electrical and Computer Engineering Labs during the COVID-19 Pandemic. IEEE International Conference on Engineering, Technology and Education (IEEE TALE), Wuhan, Peoples Republic of China, 5-8 December 2021. Piscataway, NJ, United States: Institute of Electrical and Electronics Engineers. doi: 10.1109/TALE52509.2021.9678716

Managing Hands-on Electrical and Computer Engineering Labs during the COVID-19 Pandemic

2013

Conference Publication

An evidence-based approach to designing a first year Electrical Engineering Course

Bergmann, Neil, O'Shea, Peter, Terrill, Philip and Sutton, Peter (2013). An evidence-based approach to designing a first year Electrical Engineering Course. AAEE 2013: 24th Annual Conference of the Australasian Association for Engineering Education, Gold Coast, QLD, Australia, 8-11 December 2013. Nathan, QLD, Australia: Griffith School of Engineering, Griffith University.

An evidence-based approach to designing a first year Electrical Engineering Course

2012

Conference Publication

Using quicksand to improve debugging practice in post-novice level students

Fenwick, Joel and Sutton, Peter (2012). Using quicksand to improve debugging practice in post-novice level students. Fourteenth Australasian Computing Education Conference (ACE2012), Melbourne, Australia, 30 January - 2 February 2012. Sydney, Australia: Australian Computer Society.

Using quicksand to improve debugging practice in post-novice level students

2011

Conference Publication

A unified emulation/simulation environment for reconfigurable system-on-chip development

Crosthwaite, Peter, Williams, John and Sutton, Peter (2011). A unified emulation/simulation environment for reconfigurable system-on-chip development. 2011 International Conference on Field-Programmable Technology, New Dehli, India, 12-14 December 2011. Piscataway, NJ, United States: IEEE. doi: 10.1109/FPT.2011.6132690

A unified emulation/simulation environment for reconfigurable system-on-chip development

2009

Conference Publication

Targeted configurable caches

Shield, John, Sutton, Peter and Williams, John (2009). Targeted configurable caches. 8th International Conference on Field-Programmable Technology, Sydney , Australia, 9-11 December 2009. Piscataway NJ, USA: IEEE. doi: 10.1109/FPT.2009.5377674

Targeted configurable caches

2009

Conference Publication

Design exploration for FPGA-based multiprocessor architecture: JPEG encoding case study

Wu, Jason, Williams, John, Bergmann, Neil and Sutton, Peter (2009). Design exploration for FPGA-based multiprocessor architecture: JPEG encoding case study. 17th IEEE Symposium on Field Programmable Custom Computing Machines, Napa, California, 5-7 April 2009. Piscataway NJ United States: IEEE. doi: 10.1109/FCCM.2009.7

Design exploration for FPGA-based multiprocessor architecture: JPEG encoding case study

2009

Conference Publication

Profile driven data-dependency analysis for improved high level language hardware synthesis

Crosthwaite, Peter, Williams, John and Sutton, Peter (2009). Profile driven data-dependency analysis for improved high level language hardware synthesis. 2009 International Conference on Field-Programmable Technology, Sydney , Australia, 9-11 December 2009. Piscataway NJ USA: IEEE. doi: 10.1109/FPT.2009.5377672

Profile driven data-dependency analysis for improved high level language hardware synthesis

2007

Conference Publication

Analysis of kernel effects on optimisation mismatch in cache reconfiguration

Shield, J., Sutton, P. and Machanick, P. (2007). Analysis of kernel effects on optimisation mismatch in cache reconfiguration. 2007 International Conference on Field Programmable Logic and Applications (FPL 2007), Amsterdam, The Netherlands, 27th - 29th August, 2007. New Jersey, USA: IEEE. doi: 10.1109/FPL.2007.4380732

Analysis of kernel effects on optimisation mismatch in cache reconfiguration

2007

Conference Publication

Operating system integration and performance of a multi stream cipher architecture for reconfigurable system-on-chip

Wee, C.M., Sutton, P.R. and Bergmann, N.W. (2007). Operating system integration and performance of a multi stream cipher architecture for reconfigurable system-on-chip. 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007), California, USA, 23-25 April, 2007. Piscataway, NJ, USA: IEEE. doi: 10.1109/FCCM.2007.19

Operating system integration and performance of a multi stream cipher architecture for reconfigurable system-on-chip

2007

Conference Publication

Dynamic cache switching in reconfigurable embedded systems

Shield, J, Sutton, P. and Machanick, P. (2007). Dynamic cache switching in reconfigurable embedded systems. 2007 International Conference on Field Programmable Logic and Applications (FPL 2007), Amsterdam, The Netherlands, 27th - 29th August, 2007. New Jersey, USA: IEEE. doi: 10.1109/FPL.2007.4380634

Dynamic cache switching in reconfigurable embedded systems

2006

Conference Publication

Multi stream cipher architecture for reconfigurable system-on-chip

Wee, C. M., Sutton, P R, Bergmann, N W and Williams, J A (2006). Multi stream cipher architecture for reconfigurable system-on-chip. 2006 International Conference on Field Programmable Logic and Applications, Madrid, Spain, 28-30 August, 2006. Spain: IEEE Circuits and Systems Society. doi: 10.1109/FPL.2006.311310

Multi stream cipher architecture for reconfigurable system-on-chip

2006

Conference Publication

Context-enhanced authentication for infrastructureless network environments

Wishart, R. G., Indulska, J., Portmann, M. and Sutton, P. R. (2006). Context-enhanced authentication for infrastructureless network environments. Third International Conference on Ubiquitous Intelligence and Computing, Wuhan, China, 3-6 September, 2006. Berlin: Springer-Verlag Berlin. doi: 10.1007/11833529_94

Context-enhanced authentication for infrastructureless network environments

2006

Conference Publication

VPN acceleration using reconfigurable system-on-chip technology

Wee, C. M., Sutton, P R, Bergmann, N W and Williams, J A (2006). VPN acceleration using reconfigurable system-on-chip technology. 14th Annual IEEE Symposim on Field-Programmable Custom Computing Machines, Napa, California, 24-26 April, 2006. USA: IEEE. doi: 10.1109/FCCM.2006.72

VPN acceleration using reconfigurable system-on-chip technology

2005

Conference Publication

An FPGA network architecture for accelerating 3DES - CBC

Wee, C. M., Sutton, P. R. and Bergmann, N. W. (2005). An FPGA network architecture for accelerating 3DES - CBC. 15th International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, 24-26 August 2005. Piscataway, N.J.: IEEE. doi: 10.1109/FPL.2005.1515806

An FPGA network architecture for accelerating 3DES - CBC

2005

Conference Publication

A post-compilation register reassignment technique for improving hamming distance code compression

Ros, Montserrat and Sutton, Peter (2005). A post-compilation register reassignment technique for improving hamming distance code compression. CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, San Francisco, CA, U.S.A., 24-27 September 2005. New York, NY, U.S.A.: ACM Press. doi: 10.1145/1086297.1086311

A post-compilation register reassignment technique for improving hamming distance code compression

2004

Conference Publication

A hamming distance based VLIW/EPIC code compression technique

Ros, M. B. and Sutton, P. R. (2004). A hamming distance based VLIW/EPIC code compression technique. The International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES 2004), Washington, U.S.A., 22-25 September 2004. New York, U.S.A.: ACM Press. doi: 10.1145/1023833.1023853

A hamming distance based VLIW/EPIC code compression technique

2004

Conference Publication

A hamming distance based VLIW/EPIC code compression technique

Ros, Montserrat and Sutton, Peter (2004). A hamming distance based VLIW/EPIC code compression technique. CASES 2004: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, Washington, DC United States, 22 - 25 September 2004. ACM.

A hamming distance based VLIW/EPIC code compression technique

2004

Conference Publication

Partial character decoding for improved regular expression matching in FPGAs

Sutton, P. R. (2004). Partial character decoding for improved regular expression matching in FPGAs. The 2004 IEEE International Conference on Field-Programmable Technology, Brisbane, 6-8 December, 2004. Piscataway, NJ: The Institute of Electrical and Electronics Engineers. doi: 10.1109/FPT.2004.1393247

Partial character decoding for improved regular expression matching in FPGAs

2004

Conference Publication

Architectural tradeoffs in reconfigurable computer for Monte Carlo based simulation of sintering

Postula, A. J., Sutton, P. R., Harrington, D. and Sutton, R. A. (2004). Architectural tradeoffs in reconfigurable computer for Monte Carlo based simulation of sintering. The Work in Progress Session, Rennes, France, 1-4 September, 2004. Austria: SEA Publications.

Architectural tradeoffs in reconfigurable computer for Monte Carlo based simulation of sintering

2004

Conference Publication

Code compression based on operand-factorization for VLIW processors

Ros, M. B. and Sutton, P. R. (2004). Code compression based on operand-factorization for VLIW processors. The Data Compression Conference 2004 (DCC 2004), Snowbird, Utah, U.S.A., 23-25 March 2004. Los Alamitos, California, U.S.A.: IEEE Computer Society. doi: 10.1109/DCC.2004.1281535

Code compression based on operand-factorization for VLIW processors

Past funding

  • 2017 - 2018
    TeamAnneal Stage Two: A Web Service for Purposeful Student Team Creation
    UQ Teaching Innovation Grants
    Open grant
  • 2015 - 2016
    TheJourneyMaker: Enhancing curriculum design, program analytics and the student experience
    Technology-Enhanced Learning Grants
    Open grant
  • 2008 - 2009
    Assessment policy and impact on practice: sharpening the policy review process in Australian universities
    ALTC Priority Projects
    Open grant
  • 2007 - 2009
    Concept Inventory Development for computer and Digital Systems
    UQ Teaching & Learning Strategic Grants
    Open grant
  • 2004 - 2007
    Reconfigurable System-on-Chip for Computer Network Appliances
    ARC Linkage Projects
    Open grant
  • 2003
    Reconfigurable Computer for Simulation of Sintering At the Atomic Level
    University of Queensland Research Development Grants Scheme
    Open grant
  • 2000
    Efficient Hardware Compilation for Reconfigurable Computing.
    UQ Early Career Researcher
    Open grant
  • 1999
    Design process improvement for reconfigurable computing
    UQ New Staff Research Start-Up Fund
    Open grant

Availability

Associate Professor Peter Sutton is:
Available for supervision

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Available projects

  • Engineering Education

    I'm interested in many aspects of Engineering and Computer Science Education, particularly technology-enhanced learning. Contact me to discuss ideas!

Supervision history

Completed supervision

Enquiries

Contact Associate Professor Peter Sutton directly for media enquiries about:

  • Computer networks
  • Computer operating systems
  • Computing - reconfigurable
  • Education - engineering
  • Electronic design automation
  • Embedded systems
  • Engineering education
  • Field programmable gate arrays FPGAs
  • Reconfigurable computing

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